Ted Chun-Chung Yang

Ted Chun-Chung Yang

Honorany Distinguished chair professor

Mail

Education：

  • 美國伊利諾理工學院 計算機科學系 博士
  • 美國華盛頓州立大學 計算機科學系 碩士
  • 國立成功大學 電機工程系 學士

Research Interest：

  • Computer Architecture
  • Fault-Tolerant Computing
  • Communication Systems
  1. Che-Wun Chiou and Ted C. Yang, "A Fast Base-K Logarithm with Redundant Representation," Journal of Information Science and Engineering, PP. 429~437, 2005-03.
  2. Che Wun Chiou, Jim-Min Lin, Ted C. Yang, "Testable Design of Inverter-Free PLAs," WSEAS Transaction on Electronics, 1/3, PP. 585~593, 2004-07. (EI)
  3. Jyh-Ming Huang and Ted C. Yang, "Fault-Tolerant Multi destination Multicast Based on Hierarchical Block Ring," The Int. J. of Parallel and Distributed Systems and Networks, Vol. 5, No. 3, PP. 89~97, 2002-06. (SCIE)
  4. Che-Wun Chiou and Ted C. Yang, "Majority-voting Approach for Common-multiplicand Multiplication Algorithm," The Journal of Ching-Ying Institute of Technology, Vol. 22, No. 2, PP. 53~56, 2002-02.
  5. L. Wang and Ted C. Yang, "On the Boosting of Instruction Scheduling by Renaming," The Journal of Supercomputing,, Vol. 19, No. 2, PP. 173~197, 2001-06.
  6. J. M. Huang and Ted C. Yang, "Multidimensional Fault Tolerance in Cube-Connected Cycles Architecture," International Journal of Computers and Applications, Vol.22, No.3, PP. 140~150, 2000-09. (SCIE)
  7. L. Wang and Ted C. Yang, "A Compiler-Based Speculative Execution Scheme for ILP Enhancement," Journal of Information Science and Engineering, Vol. 16, No. 1, PP. 1~12, 2000-01. (SCIE)
  8. L. Wang and Ted C. Yang, "Compiler/Hardware Co-design for Instruction Boosting in ILP Processors," IEE Proceedings-Computers and Digital Techniques, Vol. 146, No. 6, PP. 269~274, 1999-11.
  9. 楊濬中, 王壘, "極長指令集處理機設計原理概述," 電子月刊, 六月號, 第35期, PP. 72~75, 1998-06.
  10. C.W. Chiou and Ted C. Yang, "Parallel Modular Multiplication with Table Look-Up," International Journal of Computer Mathematics, Vol.69,, PP. 49~55, 1998-01.
  11. Jyh-Ming Huang, Chung-Liang Yen, Chia-Cheng Liu, and Ted C. Yang, "A Novel Broadcast Approach for Multi-Port Wormhole Torus Networks," Information Engineering, vol.34, PP. 36~47, 1998-01.
  12. C. W. Chiou, and Ted C. Yang, "Self-Purging Redundancy with Adjustable Threshold for Tolerating Multiple Module Failures," IEE Electronic Letters, Vol. 31, No. 11, PP. 930~931, 1995-01.
  13. C. W. Chiou and Ted C. Yang, "Iterative Modular Multiplication Algorithm Without Magnitude Comparison," IEE Electronic Letters, Vol.30, No. 24, PP. 2017~2018, 1994-01.
  14. C. W. Chiou and Ted C. Yang, "A Division Algorithm Without Number Comparison," International Journal Computer Mathematics, Vol. 54, PP. 53~56, 1994-01. (SCIE)
  15. H. Y. Lo and Ted C. Yang, "Balanced High-Speed Residue Number VLSI Multiplier with Error Detection," IEE Proceedings, Vol. l38, No. 3, PP. 421~423, 1991-01. (SCIE)
  16. Ted C. Yang and C. W. Chiou, "Random Pattern Testability Based on Critical Path Tracing," International Journal of Computer Applications in Technology, Vol. 3, No. 2, PP. 88~91, 1990-01. (EI)
  17. Ted C. Yang and C. W. Chiou, "Testable PLA Design with Minimal Overhead," Integration, the VLSI Journal, The Netherlands, Vol. 10, PP. 9~18, 1990-01. (EI)
  18. Ted C. Yang and C. W. Chiou, "Universal Syndrome-Testable Design of Programmable Logic Arrays," Integration, the VLSI Journal, The Netherlands, Vol. 10, PP. 3~8, 1990-01. (EI)
  19. Ted C. Yang, C. W. Chiou, and J. M. Lin, "On the Fast Generation of Base-K Logarithm," International Journal of Computer Mathematics, Vol. 30, PP. 133~141, 1989-08. (EI)
  1. J.-M. Huang, C.-H. Huang, and T. C. Yang,"Tensor Product Modeling of Fault Tolerant Multiprocessor Architectures ," Proceedings of the 2002 International Conference on Parallel and Distributed Systems (ICPADS2002), 495-500, 2002-12. NCU, Chung-Li, Taiwan .
  2. Jyh-Ming Huang and Ted C. Yang,"Multidestination Multicast Communication Based on Hierarchical Block Rings ," The ISCA 14th International Conference on Parallel and Distributed Computing Systems, pp. 31-36, 2001-08. Richardson, Texas USA .
  3. L. Wang and Ted C. Yang,"A Theoretical Analysis for Instruction Boosting in ILP Processors ," The 2001 International Symposium on Information Systems and Engineering (ISE'2001), 121-128, 2001-06. USA .
  4. Jyh-Ming Huang and Ted C. Yang,"A Hierarchical Block-Ring Based Multicast Communication Scheme ," Proceedings of The 2001 International Conference on Parallel and Distributed Techniques and Applications, 305-311, 2001-06. Las Vegas, Nevada, USA .
  5. Jyh-Ming Huang and Ted C. Yang,"A Dynamic Fault-Tolerant Mesh Architecture ," the 7th International Workshop on Parallel and Distributed Real-Time Systems, pp. 418-424, 1999-04. San Juan, Puerto Rico .
  6. Ted C. Yang and L. Wang,"On the Design and Modeling of a Homogeneous VLIW Architecture ," International Conference on Computer Architecture, ICS, 82-89, 1996-12. ICS .
  7. Ted C. Yang, Kae-Fen Hwang, Jiunn-Wen Jou, and Chia-Cheng Liu,"An SCSI-Based Adaptive Router in Torus Network ," International Conference on Computer Architecture, ICS, 241-252, 1996-12. ICS .
  8. L. Wang, J. W. Jou, H. Y. Hsu, and Ted C. Yang,"A Dual-Mode Homogeneous VLIW Computer and Its System Features ," the Workshop on CPU Research and Development, 65-72, 1995-05. National Chiao-Tung Univ .
  9. C. R. Huang, J. W. Jou, L. Wang, and Ted C. Yang,"On Performance Evaluation of Shift Scheduling and HVLIW Architecture ," the first Workshop on Compiler Techniques for High-Performance Computing, 110-116, 1995-02. NCU, Taiwan .
  10. C. P. Lin, Y. Huang, and Ted C. Yang,"Interconnection Networks for a Homogeneous Very Long Instruction Word Architecture ," International Computer Symposium, 824-830, 1992-12. FCU, Taiwan .
  11. W. C. Tseng, L. Wang, H. Y. Hsu, and Ted C. Yang,"The Design of Asymmetrical Register Structure for VLIW/FC ," International Computer Symposium, 143-149, 1992-12. FCU, Taiwan .
  12. J. Y. Yu, Kuo-Kuei Lin, and Ted C. Yang,"On Shift Scheduling of Homogeneous VLIW Architectures ," International Computer Symposium, 705-712, 1992-12. FCU, Taiwan .
  13. C. W. Chiou, H. C. Wu, and Ted C. Yang,"Random Testing of a RISC-Type Processor ," the ISMM International Symposium on Computer Applications in Design, Simulation, and Analysis, 90-93, 1990-01. New Orleans, LA., USA .
  14. C. C. Chang, G. G. Lin, H. Y. Hsu, H. C. Wu, and Ted C. Yang,"RISC/B Virtual Memory Management and Cache Design ," the ISMM International Symposium on Computer Applications in Design, Simulation, and Analysis, 1990-01. New Orleans, LA., USA .
  15. Y. Y. Chen and Ted C. Yang,"Modeling and Performance Evaluation of RISC/B Processor ," the First International Conference on Systems Integration, 1-11, 1990-01. Morristown, NJ., USA .
  16. C. W. Chiou and Ted C. Yang,"Fully Testable PLA Design with Minimal Extra Input ," the European Design Automation Conference on Systems Integration, 633-638, 1990-01. Glasgow, Scotland .
  17. C. T. Hwang, W. B. Tsay, C. H. Chang, A. C. Liu, and Ted C. Yang,"Error Recovery and Data Consistency in a Fault-Tolerant Distributed System ," 1989 ISMM International Conference on Intelligent Distributed Processing, 45-48, 1989-08. Fort Lauderdalem, USA .
  18. Kuen C. Chern, H.Y. Hsu, K. K. Lin, Y. Huang and Ted C. Yang,"Design Tradeoffs in RISC/B Processor ," 1989 International Computer Conference, 10-14, 1989-04. Hong Kong .
  19. J. Wang, H. Y. Hsu, K. K. Lin, and Ted C. Yang,"Multi-Coprocessor Parallel Architecture for RISC/B ," the 1989 National Computer Conference,, 154-163, 1989-01. Taiwan .
  20. Y. Y. Chem, K. C. Chem, and Ted C. Yang,"Performance Analysis of RISC/B Processor ," the 1988 International Computer Symposium, 215-220, 1988-12. Taiwan .
  21. S. W. Tai, Y. S. Lee, and Ted C. Yang,"Optimizing Delayed Loads and Delayed Branches for RISC/B ," the 1988 International Computer Symposium, 182-187, 1988-12. Taiwan .
  22. Y. Hwang, K. C. Chem, and Ted C. Yang,"Design Decisions on RISC/B Execution Strategy ," the 1988 ISMM International Conference on Mini and Microcomputers, 6-10, 1988-01. . .
  23. S. W. Tai, K. K. Lin, and Ted C. Yang,"Code Reorganization and Register Allocation under the RISC Pipeline Environment ," the 1987 National Computer Symposium, 47-56, 1987-12. Taiwan .
  24. H. Y. Hsu, S. C.Chen, K. C.Chen, C. T.Chen, and Ted C. Yang,"On the Design of RJSC/B Instruction Pipeline ," the 1987 National Computer Symposium, 66-75, 1987-12. Taiwan .
  25. H. Y. Hsu, Y. Hwang, K. C. Chem, C. T. Chem, and Ted C. Yang,"Control Path and Data Path Design for RISC/B ," the 1987 National Computer Symposium, 57-65, 1987-12. Taiwan .
  26. J. C. Chen, K. K. Lin, H. Y. Hsu, and Ted C. Yang,"The Design and Implementation of an Event-Driven Logic Simulator ," the 1987 National Computer Symposium, 538-544, 1987-12. Taiwan .
  27. Ted C. Yang and C. W. Chiou,"Syndrome Testable Design with Minimal Input Insertion for Multiple Faults ," Proceedings of the 1987 International Phoenix Conference on Computers and Communications, 100-104, 1987-05. . .
  28. C. W. Chiou and Ted C. Yang,"A General Reconfigurable Redundancy System ," the 1987 International Phoenix Conference on Computers and Communications, 84-88, 1987-03. . .
  29. Ted C. Yang and C. W. Chiou,"Design of Self-Checking PLAs Using Alternating Logic ," the 1987 International Test Conference, 189-196, 1987-01. . .
  30. Ted C. Yang and C. W. Chiou,"A State-Based Testability Measure for Digital Circuits ," the International Computer Symposium, 174-179, 1986-12. Taiwan .
  31. H. Y. Hsu, Y. Hwang and Ted C. Yang,"The Sharing of Register File in RISC Architectures ," the International Computer Symposium, 288-297, 1986-12. Taiwan .
  32. S. R. Tsai and Ted C. Yang,"A Dynamic Job Scheduler for distributed Multiaccess Networks ," the International Computer symposium, 1573-1582, 1986-12. Taiwan .
  33. S. M. Guo and Ted C. Yang,"Software Implemented Personal Computer Network ," the National Computer Symposium, 944-951, 1985-12. Taiwan .
  34. S. S. Hong and Ted C. Yang,"Reliability and Availability Estimation of a Reliable Microprocessor-Based System ," the National Computer Symposium, 300-307, 1985-12. Taiwan .
  35. C. W. Chiou and Ted C. Yang,"On-line Error Detection in VLSI-Implemented Interconnection Network ," the National Computer Symposium, 875-887, 1985-12. Taiwan .
  36. Paul C. P. Lin and Ted C. Yang,"A Microcomputer Based Control System for an Intelligent Robot ," the National Computer Symposium, 1552-1565, 1985-12. Taiwan .
  37. S. R. Tsai and Ted C. Yang,"A Study on Load Balancing of Distributed Computer Systems ," the National Computer Symposium, 59-69, 1985-12. Taiwan .
  38. Ted C. Yang and O. F. Chen,"Reliability Modeling and Analysis of a Generalized Responsive Redundancy Scheme ," the IEEE International Conference on Computer Design: VLSI in Computers, 514-517, 1985-01. . .
  39. Ted C. Yang and O. F. Chen,"Reliability Modeling and Analysis of a Two-Dimensional Redundancy Scheme ," the 4th Hungarian Computer Science Conference, 1985-01. Hungary .
  40. S. S. Horng and Ted C. Yang,"A Reliable Microprocessor-Based Traffic Controller ," the International Computer Symposium, 1472-1481, 1984-12. Taiwan .
  41. K. K. Chow, W. B. Leonard and Ted C. Yang,"A Wavelength Division Multiplexed(WDM) Optical Data Bus for Future Military ," the AIAA/IEEE 6th Digital Avionics System Conference, 399-404, 1984-08. . .
  42. Ted C. Yang and J. Liu,"A Reliable Multi-Microprocessor System ," the 1984 International Conference on Industrial Electronics Control and Instrumentation, 1169-1176, 1984-08. Tokyo, Japan .
  43. Ted C. Yang and A. S. Wojcik,"A Study of Reduced Dependence In Multi-valued Sequential Machines ," the 13th International Symposium on MVL, 12-20 (EI), 1983-01. . .
  44. Ted C. Yang,"A Microprocessor-Based Fault Tolerant Traffic Controller ," 1983 Symposium on Automatic Control Proceedings, 1983-01. . .
  45. Ted C. Yang,"L-rep:A Reliability Estimation Program ," the 4th Digital Avionics System Conference, 1981-01. . .
  46. Ted C. Yang and A. S. Wojcik,"Parallel and Serial Decompositions of Multi-valued Sequential Machines ," the 8th International Symposium on Multi-valued Logic, 179-186 (EI), 1978-01. . .
  47. Ted C. Yang,"A gate-Level Logic Simulator for 3-Valued Switching Networks ," the 7th International Symposium on MVL, 47-50, 1977-08. . .
  48. Ted C. Yang and A. S. Wojcik,"A Minimization Algorithm for Ternary Switching Functions ," the 6th International Symposium on Multi_Valued Logic, 241-255, 1976-08. . .
  1. 技術報告/Ted C. Yang/Consistency and Capability Checking of MMU/Cache in RISC/B/ Information Engineering, No.24/中華民國/1988-01-01/None/ /
  2. 技術報告/Ted C. Yang/Modeling and Preliminary Performance Evaluation of RISC/B/ Information Engineering, No.24/中華民國/1988-01-01/None/ /
  3. 技術報告/Ted C. Yang/Implementating and Test Report of RISC/B Prototype/ Information Engineering, No.24/中華民國/1988-01-01/None/ /
  4. 技術報告/Ted C. Yang/Path and Testability Design for RISC/B/ Information Engineering, No.24/中華民國/1988-01-01/None/ /
  5. 技術報告/Ted C. Yang/Multiple Windows Register File for Multiple Tasks/ Information Engineering, No.23/中華民國/1987-01-01/None/ /
  6. 技術報告/Ted C. Yang/A dBASE III - Based Business Cards System/ Information Engineering, NO.23/中華民國/1987-01-01/None/ /
  7. 技術報告/Ted C. Yang/Experience in ISPS Simulation on RISC Architecture/ Information Engineering, No.23/中華民國/1987-01-01/None/ /
  8. 技術報告/Ted C. Yang/Design and Implementation of Dynamic Process Scheduler for Multiprocessor System/ Information Engineering, No.22/中華民國/1986-01-01/None/ /
  9. 技術報告/Ted C. Yang/A Reliable Multi-Microprocessor System/ Information Engineering, No.21/中華民國/1985-01-01/None/ /
  10. 技術報告/Ted C. Yang/An Optically Linked Distributed Computer System/ Information Engineering, No.20/中華民國/1984-01-01/None/ /
  11. 技術報告/Ted C. Yang/A Design of Interconnect Computer Network/ Information Engineering, No.19/中華民國/1983-01-01/None/ /
  12. 技術報告/Ted C. Yang/Interconnect Technology/ Lockheed Missiles & Space Co./美國/1981-08-01/None/ /
  13. 技術報告/Ted C. Yang/Fault-Tolerant Spaceborne Computer Requirements/ Lockheed Missiles & Space Co./美國/1980-01-01/None/ /
  14. 技術報告/Ted C. Yang/The Decomposition of Multiple-Valued Sequential Machines/ Technical Report,IIT, Chicago/美國/1977-01-01/None/ /
  15. 技術報告/Ted C. Yang/A Study Report of the IMS/360/ Technical Report 76-2,IIT/美國/1976-01-01/None/ /
  16. 專業書籍/Ted C. Yang/12860-An Interface Makes an INTERDATA/4 look like an IBM 360/67 Selector Channel/ Washington State University/美國/1971-01-01/None/ /
  1. 結餘款再運用計畫/1995-01~1995-12/ NSC 84-2745-X-035-001/主持人
  2. 分散式電腦系統下錯誤回復之研究(Ⅰ)/1976-12~1977-11/ NSC 77-0408-E035-03/主持人
  3. 分散式電腦系統下錯誤回復之研究(Ⅱ)/1977-11~1978-11/ NSC 78-0408-E035-03/主持人
  4. 指令階層平行處理機的推測執行之研究/1997-08~1998-07/ NSC87-2213-E-035-028/主持人
  5. 大量平行處理電腦系統之研製-總計劃(II)/1996-08~1997-07/ NSC86-2213-E-035-021/主持人
  6. 大量平行處理電腦系統之研製總計畫(Ⅰ)/1995-08~1996-07/ NSC 85-2213-E-035-016/主持人
  7. 高效能計算VLIW架構處理機及編譯器之研究/1979-08~1980-07/ NSC 80-0408-E-035-01/主持人
  8. 計算機工作站RISC型式處理機之設計與製作(Ⅲ)/1976-12~1977-11/ NSC 77-0408-E035-04/主持人
  9. 高效能計算VLIW架構處理機及編譯器之研究(Ⅱ)/1991-08~1992-07/ NSC81-0408-E-035-03/主持人
  10. 計算機工作站RISC型式處理機之設計與製作(二)/1975-12~1976-11/ NSC 76-0408-E-035-02/主持人
  11. 高效能計算VLIW架構處理機及編譯器之研究(Ⅲ)/1992-08~1993-07/ NSC82-0408-E-035-009/主持人
  12. 高效能計算VLIW架構處理機及編譯器之研究(四)/1993-08~1994-07/ NSC83-0408-E-035-027/主持人
  13. 一個VLIW處理器的晶片設計與視覺化編譯環境之建立/1994-08~1995-07/ NSC 84-2215-E-035-008/主持人
  14. 以連結環路為基礎並具可容錯性及可擴充性的計算機架構之研究/1997-08~1998-07/ NSC87-2213-E-035-029/主持人
  1. 84/國科會甲種獎勵 /行政院國科會/ 1995-08-01/SELF-PURGING REDUNDANCY WITH ADJNSTABLE THRESHOLD FOR TOLERATING MULTIPLE MODULE FAILURES
  2. 82/國科會甲種獎勵 /行政院國科會/ 1993-08-01/高效能計算VLIW架構處理機及編譯器之研究(IV)
  3. 81/國科會優等獎勵 /行政院國科會/ 1992-08-01/以症候設計可測程式邏輯陣列之研究
  4. 80/國科會甲種獎勵 /行政院國科會/ 1991-08-01/追䎪決定性線路以計算可測性之研究
  5. 79/國科會甲種獎勵 /行政院國科會/ 1990-08-01/可測試程式邏輯陣列之設計
  6. 78/國科會甲種獎勵 /行政院國科會/ 1989-08-01/RISC/B處理機執行策略之抉擇
  7. 77/國科會甲種獎勵 /行政院國科會/ 1988-08-01/以交換邏輯設計自測之可程式邏輯陣列
  8. 76/國科會甲種獎勵 /行政院國科會/ 1987-08-01/以最少額外輸入偵測複錯之設計
  9. 75/國科會甲種獎勵 /行政院國科會/ 1986-08-01/通用反應式複聯結構之可靠性模型與分析
  1. 91/逢甲大學論文著作獎勵優良獎/逢甲大學/ 2002-11-15/On the Boosting of Instruction Scheduling by Renaming
Last update：2024-11-21, 9:02 a.m. Next update：2024-11-22, 9 a.m.