陳啟鏘

教授

課表時間

學歷

  • 美國俄亥俄州立大學 電機工程學系 博士
  • 美國俄亥俄州立大學 電機工程學系 碩士
  • 國立成功大學 電機工程學系 學士

專長

  • 單晶片系統設計與應用
    SOC Design and Applications
  • 影像與視訊處理
    Image and Video Processing
  • 計算機算術與VLSI設計
    Computer Arithmetic and VLSI Design

校內經歷

  • 招生組 組長
  • 研究生教務組 組長
  • 資訊工程學系 教授
  • 資訊工程學系 系主任
  • 資訊工程學系(所) 副教授

校外經歷

  • 台灣國際標準電子公司 產品開發部 設計工程師

論文及參與計畫

  1. 陳啟鏘*, "High-order Taylor series approximation for efficient computation of elementary functions," IET Computers & Digital Techniques, Vol. 9, Iss. 6, pp. 328–335, 2015-11. (SCIE)
  2. Rui-Lin Chen,Chichyang Chen, "Efficient computation of very high effective-precision exponential function with additive normalization method," Journal of the Chinese Institute of Engineers, vol.34, no. 7, 2011-01. (SCIE)
  3. Chichyang Chen, "Error analysis of LNS addition/subtraction with direct-computation implementation," IET Journals-Computers and Digital Techniques, 3/4, PP. 329~337, 2009-07. (SCIE)
  4. Chichyang Chen, "Error analysis of LNS addition/subtraction with direct-computation implementation," IET Journals-Computers and Digital Techniques, 3/4, PP. 329~337, 2009-07. (SCIE)
  5. 陳啟鏘, "對數數字系統算術與傳統浮點數及定點數算術的比較研究(III)," 工程科技通訊, 94期, PP. 124~128, 2007-10.
  6. Chichyang Chen and Rui-Lin Chen, "Performance-Improved computation of very large word-length LNS addition/subtraction using signed-digit arithmetic," Journal of Information Science and Engineering, Vol. 23, No. 5, PP. 1579~1596, 2007-09. (SCIE,EI)
  7. Chichyang Chen, Rui-Lin Chen, and Ming-Hwa Sheu, "A hardware algorithm for fast logarithmic computation with exponential convergence rate," Journal of the Chinese Institute of Engineers, 28/4, PP. 749~752, 2005-08. (SCIE)
  8. Chichyang Chen, Hsin-Lin Yen and Ming-Hwa Sheu, "Design of a New Divider/Multiplier Fused Unit for Floating-Point Arithmetic," International Journal of Electrical Engineering, Volume 11, No. 3, PP. 239~246, 2004-08.
  9. Ming-Hwa Sheu, Su-Hon Lin, Chichyang Chen, and Shyue-Wen Yang, "An efficient VLSI Design for a Residue to Binary Converter for General Balance Moduli (2^n-3 ,2^n+1 ,2^n-1 ,2^n+3)," IEEE Transactions on Circuits and Systems II-Analog and Digi, vol 51, PP. 152~155, 2004-03. (SCIE)
  10. Hao-Yung Lo, Hsiu-Feng Lin, Chichyang Chen, Jenshiuh Liu and Chia-Cheng Liu, "Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers," JOURNAL OF ELECTRONIC TESTING: Theory and Applications, Vol.19, PP. 245~269, 2003-10. (SCIE)
  11. Chichyang Chen, Rui-Lin Chen and Ming-Hwa Sheu, "A Fast Additive Normalization Method for Exponential Computation," Proceedings of Euromicro Symposium on Digital Dystem Design, , PP. 286~293, 2003-09. (SCIE)
  12. Nansen Chen，Kevin Chiang，T.D. Her，Yeong-Lin Lai and Chichyang Chen, "Electrical Characterization and structure investigation of quad flat non-lead package for RFIC applications," Solid State Electronics, vol.47, PP. 315~322, 2003-08.
  13. Chichyang Chen, L.-A. Chen and C.-J. Cheng, "Architectural design of a fast floating-point multiplication-add fused unit using signed-digit addition," IEE Proceedings -Computer and Digital Techniques, Vol. 149, No. 4, 2002-07. (SCIE)
  14. Chichyang Chen, Chiun-Wen Hsu and Te-Lung Lin, "Image prediction using face detection and triangulation," Pattern Recognition Letters, vol. 22, PP. 1347~1357, 2001-08. (SCIE)
  15. Chichyang Chen and Chiun-Wen Hsu, "Content-based hybrid DPCM/classified vector quantization for coding video telephony sequences," Journal of visual communication and image representation, vol.12, PP. 152~168, 2001-08. (SCIE,EI)
  16. Chichyang Chen, Rui-Lin Chen and Chih-Huan Yang, "Pipelined computation of very large word-length LNS addition/subtraction with polynomial hardware cost," IEEE Transactions on Computers, Vol. 49, No. 7, PP. 716~726, 2000-07. (SCIE)
  17. Chichyang Chen and C.D. Wang, "A Simple edge-preserving filter technique for constructing multi-resolution systems of images," Pattern Recognition Letters, NO.20, PP. 495~506, 1999-08. (SCIE)
  18. 陳啟鏘, "A Simple Edge-Preserving Filtering Technique for Constructing Multi-resolution Systems of Images," Pattern Recognition Letters, Vol. 20/ No.5, PP. 495~506, 1998-08. (SCIE,EI)
  19. 陳啟鏘、卓國雄、蔣序平, "Design of 32-Digit On-Line Exponential and Logarithmic Computational Units," Journal of Feng Chia University, No. 29, PP. 217~232, 1996-08.
  20. 陳啟鏘、卓國雄, "Design of 40-Digit On-Line Addition Unit in Logarithmic Number System," Journal of Feng Chinese Institute of Electrical Engineering, 1996-08.
  1. 郭哲瑋 徐崇涵 陳啟鏘,"利用語義分割與立體視覺重建三維場景 ," 第二十屆離島資訊技術與應用研討會, pp. 197-197, 2022-05. 澎湖 .
  2. M.-T. Liao* and C.-C. Chen,"利用雙眼視覺進行三維物體重建 ," 2021 第十九屆離島資訊技術與應用研討會, 2021-05., May, 2021, 2021-05. 金門大學 .
  3. 王以碩、黃偉豪、林恩宇、陳啟鏘,"改良CANNY演算法實做準確的KINECT深度影像邊緣偵測 ," 數位生活科技研討會, Number 290, 2015-06. 國立高雄第一科技大學 .
  4. 許仕明*、劉環瑀、陳啟鏘,"使用圖形處理單元加速立體視覺 ," 第十三屆離島資訊技術與應用研討會, pp. 412-416, 2014-05. 屏東 .
  5. 陳威宇，陳啟鏘*,"使用客製化指令在系統上實現快速的嵌入式人臉偵測 ," 第十二屆離島資訊技術與應用研討會, pp. 524-527, 2013-05. 金門 .
  6. 1. Chichyang Chen, Li-Wei Liu, and Jun-Wen Jou,"Software Implementation of LNS Arithmetic in an ARM Embedded System ," Proceedings of the 13th IEEE International Symposium on Consumer Electronics, 122, 2009-05. Kyoto, Japan .
  7. 2. Chichyang Chen and Tsung Che Tsai,"Application-Specific Instruction Design for LNS Addition/Subtraction Computation on an SOPC System ," Proceeding of the International conference of Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, 122, 2009-05. Pataya, Thailand .
  8. Yung Ching Yang and Chichyang Chen,"Design of an Automatic Instruction Selection Algorithm for Enhancing Arithmetic Performance ," IEEE Symposium on Low-Power and High-Speed Chips, CoolChip XI, 125-125, 2008-04. Yokohama, Japan .
  9. 盧麗娟、陳啟鏘,"Altera SOPC系統處理器傳輸方法的研究與其應用 ," 2007年系統雛型與電路設計創新應用研討會, 2007-09. 崑山科技大學，台南縣，台灣 .
  10. Chih-Yen Fan and Chi-Chyang Chen,"A comparative study of LNS and floating- point arithmetic ," 18th VLSI Design/CAD Symposium, 2007-08. Hualien, Taiwan .
  11. Chichyang Chen and Paul Chow,"Design of a versatile cost-effective hybird floating-point/LNS arithmetic processor ," ACM Great Lakes Symposium on VLSI(GLSVLSI), 540-545, 2007-03. Stresa-Lago Maggiors, Italy .
  12. Chichyang Chen,"Error analysis of large word-length LNS addition/substraction computation ," the International MultiConference of Engineers and Computer Scientists, 221-224, 2006-06. Hong Kong .
  13. Heng-Sheng Shen and Chichyang Chen,"Implementation of speech recognotion with floating-point and LNS arithmetic in an SOPC system ," the 16th VLSI Design/CAD Symposium, 2005-08. Hualien, Taiwan .
  14. Chichyang Chen and Kuo-Shen Cheng,"An efficient exponential algorithm with exponential convergence rate ," Euromicro Symposium on Digital System Design, 548-555, 2004-08. Rennes, France .
  15. Chichyang Chen, Rui-Lin Chen and Ming-Hwa Sheu,"A fast additive normalization method for exponential computation ," Euromicro Symposium on Digital System Design, 2003-09. Antalya, Turkey .
  16. Chichyang Chen and Rui-Lin Chen,"Performance-improved computation of very large word-length LNS addition/subtraction using signed-digit arithmetic ," IEEE International Conference on Application-Specific Systems, Architectures, and Processors, 337-347, 2003-07. The Hague, Netherlands .
  17. Chichyang Chen, Liang-An Chen and Jih-Ren Cheng,"Architectural design of a fast floating-point multiplication-add fused unit using signed-digit addition ," the Euromicro Symposium on Digital Systems Design, 346-353, 2001-09. Warsaw, Poland .
  18. Yung-Ling Chen and Chichyang Chen,"Design of a fast signed-digit divider for floating-point arithmetic ," the 12th VLSI Design/CAD Symposium, 2001-08. Hsin-Chu, Taiwan .
  19. Nansen Chen, Kevin Chiang, T. D. Her, Teong-Lin Lai, and Chichyang Chen,"Electrical characterization of quad flat non-lead package for RFIC applications ," the International Semiconductor Device Research Symposiu, 266-269, 2001-08. - .
  20. ChiChyang Chen,"Pipelined Computation of LNS Addition/Subtraction with Very Small Lookup Tables ," Proceedings of IEEE International Conference on Computer Design, pp. 292~297, 1998-12. Austin, Tx., USA .
  1. Happy As a Clam: 智慧文蛤養殖/2019-07~2020-02 /108-2813-C-035-020-E /主持人
  2. 使用高階泰勒級數近似法從事高效率對數數字系統算術加減法的計算/2016-08~2017-07 /MOST105-2221-E-035-061- /主持人
  3. 使用泰勒級數逼近法應用於高效率多種基本函數計算之創新性硬體架構/2013-08~2014-07 /NSC 102-2221-E-035-037- /主持人
  4. 高效率浮點數與對數數字系統算術計算之客製化指令集的設計/2012-08~2013-07 /NSC101-2221-E-035-068- /主持人
  5. 嵌入式高精密度複雜函數計算之客製化指令的設計/2010-08~2011-07 /NSC99-2221-E-035-052- /主持人
  6. 系統效率最佳化之自動算術指令選擇方法的設計及其應用（Ⅱ）/2008-08~2009-07 /NSC97-2221-E-035-043- /主持人
  7. 系統效率最佳化之自動算術指令選擇方法的設計及其應用/2007-08~2008-07 /NSC96-2221-E-035-035- /主持人
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  9. 動態可重組式計算之對數數字系統算術單元的設計—以自動語音辨認為應用實例/2005-08~2006-07 /NSC94-2213-E-035-028- /主持人
  10. 對數數字系統算術與傳統浮點數及定點數算術的比較研究(III)/2004-08~2005-07 /NSC93-2213-E-035-041- /主持人
  11. 對數數字系統與傳統浮點數及定點數算術的比較研究(II)/2003-08~2004-07 /NSC92-2213-E-035-017- /主持人
  12. 對數數字系統算術與傳統浮點數及定點數算數的比較研究(Ⅰ)/2002-08~2003-07 /NSC91-2213-E-035-017 /主持人
  13. 使用帶號位元數字系統加法設計快速浮點數乘加混合單元/2001-08~2002-07 /NSC90-2213-E-035-032 /主持人
  14. 利用一種新的陣列乘法器設計浮點數乘除法混合運算之算術單元/2000-08~2001-07 /NSC89-2215-E-035-016 /主持人
  15. 高精密度與管線式之極小查表對數數字系統加減法單元之IC設計與實作/1999-08~2000-07 /NSC89-2215-E-035-006 /主持人
  16. 使用FPGA從事管線式與小查表之對數數字系統加減法單元之硬體設計與實現/1998-08~1999-07 /NSC88-2213-E-035-003 /主持人
  17. 使用影像三角化及影像扭曲之超低位元率視訊編碼/1997-08~1998-07 /NSC87-2213-E-035-031 /主持人
  18. 離散餘旋轉換演算法在浮點數及對數數字系統的誤差分析/1997-08~1998-07 /NSC87-2213-E-035-006 /主持人
  19. 影像處理實驗用之pc介面卡的設計與製作(大專生暑期)/1997-07~1998-02 /NSC87-2815-035-044-E /主持人
  20. 連續影像中臉面特徵的自動追蹤/1996-08~1997-07 /NSC86-2213-E-035-026 /主持人
  21. 彩色影像中的臉面偵測/1995-08~1996-07 /NSC 85-2213-E-035-024 /主持人
  22. 序向運算(On-Line)對數數字系統處理器的設計/1995-02~1995-07 /NSC 84-2213-E-035-013 /主持人
  23. 序向運算對數數字系統處理器的設計/1994-02~1995-07 /NSC83-0408-E-035-007 /主持人
  24. 使用數學形態學識別重疊之物體/1993-01~1993-12 /NSC82-0113-E035-055T /主持人
  1. 大尺寸立式偏光板貼附工作站研發計畫 /2009-11~2011-05 /顧問
  2. 97年度「資通安全學程推廣計畫」 /2008-09~2009-08 /主持人
  3. 前瞻晶片系統(soC)學程計畫－系統晶片 /2008-03~2009-02 /主持人
  4. 資通安全學程推廣計畫_資通安全學程 /2007-09~2008-08 /主持人
  5. 前瞻晶片系統設計（SoC）學程計畫-系統晶片 /2007-03~2008-02 /主持人
  6. 資通安全學程推廣計畫-資通安全學程 /2006-09~2006-08 /主持人
  7. 逢甲大學95年度e三五教學卓越計畫 /2006-08~2007-07 /協同主持人
  8. 超大型積體電路與系統設計教育改進計畫─課程推廣計畫：「FPGA系統設計」課程 /2003-03~2003-12 /共同主持人
  9. 具高速算術運算能力之微控制器的設計 /2001-08~2002-07 /主持人
  1. 89/國科會甲種獎勵 /行政院國科會/ 2000-08-01/Pipelined Computation of Very Large Word-Length LNS Addition/Subtraction with Polynomial Hardware Cost
  1. 105/逢甲大學論文著作獎勵優良獎 /逢甲大學/ 2016-11-15/High-order Taylor series approximation for efficient computation of elementary functions
  2. 101/逢甲大學論文著作獎勵優良獎 /逢甲大學/ 2012-11-15/Efficient computation of very high effective-precision exponential function with additive normalization method
  3. 99/逢甲大學論文著作獎勵優良獎 /逢甲大學/ 2010-11-15/Error analysis of LNS addition/subtraction with direct-computation implementation
  4. 97/逢甲大學論文著作獎勵 /逢甲大學/ 2008-11-15/對數數字系統算術與傳統浮點數及定點數算術的比較研究(III)
  5. 97/逢甲大學論文著作獎勵優良獎 /逢甲大學/ 2008-11-15/Performance-Improved computation of very large word-length LNS addition/subtraction using signed-digit arithmetic
  6. 95/逢甲大學論文著作獎勵優良獎 /逢甲大學/ 2006-11-15/A hardware algorithm for fast logarithmic computation with exponential convergence rate
  7. 94/逢甲大學論文著作獎勵傑出獎 /逢甲大學/ 2005-11-15/An efficient VLSI Design for a Residue to Binary Converter for General Balance Moduli (2^n-3 ,2^n+1 ,2^n-1 ,2^n+3)
  8. 92/逢甲大學論文著作獎勵傑出獎 /逢甲大學/ 2003-11-15/Architectural design of a fast floating-point multiplication-add fused unit using signed-digit addition
  9. 91/逢甲大學論文著作獎勵傑出獎 /逢甲大學/ 2002-11-15/Image prediction using face detection and triangulation
  10. 91/逢甲大學論文著作獎勵傑出獎 /逢甲大學/ 2002-11-15/Content-based hybrid DPCM/classified vector quantization for coding video telephony sequences
最後更新時間：2024-12-21, 9:02 a.m. 下次更新時間：2024-12-22, 9 a.m.