陳德生

副教授

課表時間

學歷

  • 美國西北大學 電機所 博士

專長

  • VLSI 電腦輔助設計
    VLSI CAD
  • 嵌入式系統
    Embedded System
  • 智慧聯網
    Intelligent IOT

校內經歷

  • 資訊工程學系 副教授
  • 資訊工程學系(所) 助理教授
  • 資訊電機學院 秘書

校外經歷

  • 工研院 電子所 研究員
  • 美國伊利諾知識系統學院 資訊系 講師
  • 美國西北大學 電機系 研究助理

論文及參與計畫

  1. Guo-Ming Fang, Jim-Min Lin, Zeng-Wei Hong, De-Sheng Chen, and Wei-Tsong Lee, "Constructing Service-Oriented Integrated EDA Environment with Agent Technology," Journal of Internet Technology, 12/6, PP. 949~967, 2011-11. (SCIE,EI)
  2. Guo-Ming Fang, Jim-Min Lin, Zeng-Wei Hong, De-Sheng Chen, Wei-Tsong Lee, "Constructing Service-Oriented Integrated EDA Environment with Agent Technology," Journal of Internet Technology, 12(6), 2011-11. (SCIE)
  3. De-Sheng Chen*, Chang-Tzu Lin, Yi-Wen Wang, and Ching-Hwa Cheng, "Constrained Floorplanning for Modern SoC Design," Journal of Cybernetics and Systems, Vol. 1, No. 1, PP. 27~39, 2008-08.
  4. De-Sheng Chen, Chang-Tzu Lin, Yi-Wen Wang, and Ching-Hwa Cheng, "Fixed-Outline Floorplanning Using Robust Evolutionary Search," Engineering Applications of Artificial Intelligence, 20, PP. 821~830, 2007-06. (SCIE,EI)
  5. De-Sheng Chen, Chang-Tzu Lin and Yi-Wen Wang, "A Robust Genetic Algorithm for Rectangle Packing Problem," Journal of Combinatorial Optimization (JOCO), Vol. 12, 2006-05. (SCIE,EI)
  6. Chang-Tzu Lin, De-Sheng Chen and Yi-Wen Wang, "VLSI Floorplanning with Boundary Constraints Using Generalized Polish Expression," Journal of the Chinese Institute of Engineers (JCIE), Vol.29, No.3, PP. 383~389, 2006-05. (SCIE,EI)
  7. Chang-Tzu Lin, De-Sheng Chen and Yi-Wen Wang, "Modern Floorplanning with Boundary and Fixed-Outline Constraints via Genetic Clustering Algorithm," Journal of Circuits, Systems, and Computers, JCSC, Vol. 15, No. 1, PP. 107~127, 2006-02. (SCIE,EI)
  1. 杜宜霖,葉珊,嚴奕翔,陳德生,"K-Drums擊鼓體感遊戲 ," 2017 創新發明應用研討會, MDD001, 2017-11. 勤益科技大學 .
  2. 林杰昱,蔡承儒,封智翔,陳德生,"iDealer 智慧樂高發牌機 ," 2017 創新發明應用研討會, ICI001, 2017-11. 勤益科技大學 .
  3. C. H. Lin, Bo-Wei Chen, De-Sheng Chen, and Yiwen Wang,"A Modified Speech Enhancement Model Based on Deep Neural Networks ," 2017 International Conference on Applied Cognitive Computing, p.52 - p.57, 2017-07. Monte Carlo Resort .
  4. Shu-Jui Hsieh, Kuan-Hung Chen, De-Sheng Chen, and Yi-Wen Wang,"A Detection and Recognition System for Chinese Highway Traffic Panels ," 2017 International Conference on Consumer Electronics-Taiwan, p.55~p.56, 2017-06. NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY .
  5. Hong-Son Vu, Jia-Xian Guo, Kuan-Hung Chen, Shu-Jui Hsieh, and De-Sheng Chen,"A Real-Time Moving Objects Detection and Classification Approach for Static Cameras ," 2016 International Conference on Consumer Electronics-Taiwan, p.258 - p.259, 2016-05. National Chi Nan University .
  6. C. H. Lin, B. C. Yang, C. B. Duanmu, B. W. Chen, D. S. Chen, and Y. Wang,"Neural Cryptography for Secure Voice Communication using Custom Instructions ," Int'l Conf. Embedded Systems and Applications, p.57 - p.61, 2015-07. Las Vegas, Nevada .
  7. Huan-Teng Li, De-Sheng Chen, Yi-Wen Wang,"A Predict Policy Method for Word-Based Montgomery Modular Multiplication ," 2012 VLSI/CAD Symposium, 2012-08. Kenting, Taiwan .
  8. Che-Ming Chang, De-Sheng Chen, Y-Wen Wang,"A High-throughput Deblocking Filter With New Filtering Schedule ," 2012 International Conference on Electronics, Communication and Computer Science, 2012-06. Naning, China .
  9. C. Hung, H. Lin, D. Chen, Y. Wang,"ASIP Instruction Selection with the Encoding-Space Constraint for High Performance ," International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies(HEART 2012), 2012-05. Okinawa, Japan .
  10. Ginhsuan Li, Chiuyun Hung, De-Sheng Chen, and Yiwen Wang*,"Application-Specific Instruction sets Processor with Implicit Registers to Improve Register Bandwidth ," World Academy of Science, Engineering and Technology, 2011-06. Paris, France .
  11. De-Sheng Chen*, Po-Yu Chen, Yi-Wen Wang,"Hardware/Software Co-Design of NLMS Adaptive Filters on FPGA ," International Symposium on Consumer Electronics, 2011-06. Singapore .
  12. Chengpin Tseng, Chiuyun Hung, De-Sheng Chen, Kuei-Chung Chang and Yi-wen Wang*,"Application Specific Instruction set Exploration on VLIW Architectures ," International Conference on Embedded Systems and Applications, 2010-07. Las Vegas Nevada, USA .
  13. De-Sheng Chen*, Kui-Shun Chou, Yi-Wen Wang,"A New Block-Based Stochastic Adaptive Algorithm for Sparse Echo Cancellation ," The International Conference on Signal Processing Systems, 2010-07. Dalian, China .
  14. Guo-Ming Fang, Jim-Min Lin, Zeng-Wei Hong, De-Sheng Chen,"An Agent-Based Workflow System for Assisting in IC Design ," The 1st Asian Conference on Intelligent Information and Database Systems (ACIIDS 2009), 351-355, 2009-04. Dong Hoi, Vietnam .
  15. Chijie Lin, Jiying Wu, Jerung Shiu, De-Sheng Chen, and Yiwen Wang*,"Performance Improvement using Application-Specific Instructions under Hardware Constraints ," International Conference on embedded Software and Systems, 2008-07. Chengdu, China .
  16. Jiying Wu, Chijie Lin, De-Sheng Chen, Yiwen Wang*,"Memory Models for an Application-Specific Instruction-set Processor Design Flow ," International Conference on Embedded Software and Systems, 2008-07. Chengdu, China .
  17. Chang-Tzu Lin, Tai-Wei Kung, De-Sheng Chen*, Yi-Wen Wang, and Ching-Hwa Cheng,"Noise-Aware Floorplanning for Fast Power Supply Network Design ," International Symposium on Circuits and Systems, 2007-05. New Orlean, U.S.A .
  18. Wei-Chih Shen, Jyun-Sian Jhou, Ching-Hwa Cheng, De-Sheng Che,"PIPD: Power Integrity Path Delay Analysis Tool ," International Computer Symposium, 78-81, 2006-12. Taiwan, Taipei .
  19. Shengjyi Yang, Chijie Lin, Chiuyun Hung, Jiying Wu, Jiawei Chang, De-Sheng Chen, and Yi-Wen Wang,"Automatic Application-Specific Instruction Generation for SOC Processors ," 17th VLSI Design/CAD Symposium, 2006-08. Hualien, Taiwan .
  20. Chang-Tzu Lin, Tai-Wei Kung, De-Sheng Chen, Yi-Wen Wang, and Ching-Hwa Cheng,"A Novel Design Methodology for SI Aware Floorplanning Designs ," 17th VLSI Design/CAD Symposium, 2006-08. Hualien, Taiwan .
  21. Chih-Liang Chen, Hsiang-Hui Huang, Ching-Hwa Cheng, De-Sheng Chen,"Diagnose the Failure Power-Switch within Power Gating Circuit ," The 17th VLSI Design/CAD symposium, 2006-08. Hualien, Taiwan .
  22. Ching-Hwa Cheng, De-Sheng Chen, Wen-Jui Chang, Chih-Liang Chen,"All-Digital Built-in Circuit Delay Tester ," 15th IEEE North Atlantic Test Workshop, 120-129, 2006-05. USA .
  23. Hsin-Hsien Ho, Chang-Tzu Lin, De-Sheng Chen, and Yi-Wen Wang,"Multilevel Genetic Placement Algorithm for Large-Scale Mixed-Size SOC Designs ," The 16th VLSI Design/CAD Symposium, ., 2005-08. Hualien, Taiwan .
  24. 34. Chih-Liang Chen, Hsiang-Hui Huang, Ching-Hwa Cheng, De-Sheng Chen,"A Delay/Power Compromise Mixed Static/Domino Circuit Synthesizer ," The 17th VLSI Design/CAD symposium, 2005-08. Hua-Lian .
  25. Hsin-Hsien Ho, Chang-Tzu Lin, De-Sheng Chen, Yi-Wen Wang,"Modern Floorplanning with Abutment and Fixed-Outline Constraints ," ISCAS 2005, pp.6214-6217, 2005-05. Kobe, Japan .
  26. Chang-Tzu Lin, De-Sheng Chen, Yi-Wen Wang, Po-Shu Shih, and Ying-Ren Xhao,"Fixed-Outline Floorplanning with Abutment Constraints ," The 15th VLSI Design/CAD Symposium, ., 2004-08. Kenting, Taiwan .
  27. Ching-Chung Hu; De-Sheng Chen; Yi-Wen Wang,"Fast multilevel floorplanning for large scale modules ," the 2004 International Symposium on Circuits and Systems, Volume: 5 , 23-26, 2004-05. 加拿大溫哥華 .
  28. Chang-Tzu Lin, De-Sheng Chen, and Yi-Wen Wang,"Robust Fixed-outline Floorplanning Through Evolutionary Search ," IEEE/ACM 2004 Asia and South Pacific Design Automation Conference, pp 42~44, 2004-01. Yokohama, Japan .
  29. Chang-Tzu Lin, De-Sheng Chen, and Yi-Wen Wang,"Robust Fixed-outline Floorplanning Through Evolutionary Search ," 2003 VLSI Design/CAD Symposium, pp 9~12, 2003-08. 花蓮 .
  30. De-Sheng Chen, Chang-Tzu Lin, and Yi-Wen Wang,"Non-Slicing Floorplans with Boundary Constraints Using Generalized Polished Expression ," IEEE/ACM 2003 Asia and South Pacific Design Automation Conference 2003, pp 342-345, 2003-01. 日本、九州 .
  31. W.-R. Lin、M.-H. Fan、C.-H. Huang, Y.-C. Chung, and D.-S. Chen,"Synthesizing VHDL Programs from Tensor Product Formulas ," 2002 International Conference on VLSI, 134~140, 2002-06. Las Vegas, Nevada, USA .
  32. Chang-Tzu Lin、De-Sheng Chen、Yi-Wen Wang,"An Efficient Gentic Algorithm for Slicing Floorplan Area Optimizition ," IEEE ISCAS 2002, 879~882, 2002-05. USA、Phoenix .
  33. Zen-Wei Hong、Jim-Min Lin、Hewijin C. Jiau、De-Sheng Chen,"DSIAS: A Software Architecture Style for Distributed Software Integration Systems ," IEEE Compsac 2001, pp 291~296, 2001-10. Chicago, USA .
  34. Chang-Tzu Lin、De-Sheng Chen、Yi-Wen Wang、I-Tsung Chen,"A Fast Evolutational Algorithm for Slicing Floorplans ," Proceedings of Proceedings of the 12th VLSI Design/CAD Symposium, CD-ROM, 2001-08. Hsin-Chu Taiwan .
  35. De-Sheng Chen, Dar-Chang Juang, Jyuo-Min Shyu, and Ching-Yuang Wu,"A Low-power 1.2GHz 0.35um CMOS PLL ," Proceedings of AP-ASIC 2000, 99-102, 2000-08. .
  36. S. W. Chen, C. W. Hsu, Y. W. Wang, D. S. Chen, C. T. Lin, and S. F. Hwang,"VLSI implementations of a multicasting shared buffer for QoS multimedia networks ," Proceedings of the 11th VLSI Design/CAD Symposium, pp. 217-220, 2000-08. - .
  1. 專業書籍/王 壘, 袁世一, 王益文, 陳德生/ARM Cortex-M3 32位元微控制器原理與應用－HT32F1655/1656/ 全華科技圖書/ 中華民國 /2017-04-01/310/ /
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  2. 應用於多圖案微影技術之研究/2023-07~2024-02 /112-2813-C-035-080-E /主持人
  3. (深耕)精密主軸於智慧型滾齒機之應用暨推廣(2/2)/2017-10~2018-09 /MOST106-2218-E-035-011- /共同主持人
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  7. H.264 去區塊濾波器之多紋理設計/2011-08~2012-07 /NSC100-2221-E-035-041- /主持人
  8. 嵌入式系統之特定應用架構研究(III)/2011-08~2012-07 /NSC100-2221-E-035-102- /共同主持人
  9. 適用於網路回聲消除之新型可適性濾波器設計與實作/2010-08~2011-07 /NSC99-2221-E-035-095- /主持人
  10. 嵌入式系統之特定應用架構研究(II)/2010-08~2011-07 /NSC99-2221-E-035-104- /共同主持人
  11. 嵌入式系統之特定應用架構研究(I)/2009-08~2010-07 /NSC98-2221-E-035-061- /共同主持人
  12. 溫度知曉之3D平面規劃架構發展/2009-08~2010-07 /NSC98-2221-E-035-072- /主持人
  13. 適用於大型VLSI佈局問題之組合最佳化技術(I)/2007-08~2008-07 /NSC96-2221-E-035-102- /主持人
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  15. 嵌入式系統晶片之架構探究(3/3)/2006-08~2007-07 /NSC95-2221-E-035-122- /共同主持人
  16. 以數學規劃法進行多層次全域繞線/2006-08~2007-07 /NSC95-2221-E-035-131- /主持人
  17. 嵌入式系統晶片之架構探究(2/3)/2005-08~2006-07 /NSC94-2215-E-035-001- /共同主持人
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  20. 可重組式計算架構之單晶片系統(II)/2003-08~2004-07 /NSC92-2218-E-035-005- /共同主持人
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  22. 使用張量乘積理論設計VLSI電路(Ⅰ)/2002-08~2003-07 /NSC91-2213-E-035-015 /共同主持人
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  24. 演化式演算法為基礎之平面規劃設計/2001-08~2002-07 /NSC90-2215-E-035-002 /主持人
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  27. 連線導向整體繞線之研究/1999-08~2000-07 /NSC89-2215-E-035-003 /主持人
  1. 智慧停車場之車位感測及彩光指示系統 /2016-06~2017-05 /共同主持人
  2. 104年度磨課師課程推動計畫-A類新星計畫【把智慧嵌入這個大千世界】 /2015-05~2016-04 /共同主持人
  3. NFC牆壁定時開關軟體與應用程式開發 /2015-03~2015-06 /共同主持人
  4. 前瞻晶片系統(soC)學程計畫－系統晶片 /2008-03~2009-02 /共同主持人
  5. 以即時通訊系統為基礎的離散式彈內計算機架構(II) /2005-03~2005-11 /主持人
  6. 超大型積體電路與系統設計教育改進計畫─課程推廣計畫：「FPGA系統設計」課程 /2003-03~2003-12 /主持人
  1. 107/逢甲大學優良教材獎勵優等獎 /逢甲大學/ 2018-11-15/ARM Cortex-M3 32位元微控制器原理與應用－HT32F1655/1656
  2. 105/逢甲大學優良教材獎勵佳作獎 /逢甲大學/ 2016-11-15/把智慧嵌入這個大千世界
  3. 101/逢甲大學論文著作獎勵優良獎 /逢甲大學/ 2012-11-15/Constructing Service-Oriented Integrated EDA Environment with Agent Technology
  4. 97/逢甲大學論文著作獎勵傑出獎 /逢甲大學/ 2008-11-15/Fixed-Outline Floorplanning Using Robust Evolutionary Search
  5. 96/逢甲大學論文著作獎勵優良獎 /逢甲大學/ 2007-11-15/A Robust Genetic Algorithm for Rectangle Packing Problem
  6. 96/逢甲大學論文著作獎勵優良獎 /逢甲大學/ 2007-11-15/VLSI Floorplanning with Boundary Constraints Using Generalized Polish Expression
  7. 96/逢甲大學論文著作獎勵優良獎 /逢甲大學/ 2007-11-15/Modern Floorplanning with Boundary and Fixed-Outline Constraints via Genetic Clustering Algorithm
  1. Cpmplementary Metal-Oxide Semiconductor High-Frequency Ring Oscillator/發明 /106251 /2000-08~ 2018-03
  2. CMOS高頻環式振盪器/發明 /6097256 /1999-07~ 2018-03
  1. 雲端學院/把智慧嵌入這個大千世界/王 壘, 王益文, 陳德生, 袁世一/磨課師課程
最後更新時間：2024-12-21, 9:02 a.m. 下次更新時間：2024-12-22, 9 a.m.